1. Field of the Invention
This invention relates to data converters. In particular, the invention relates to digital-to-analog converters (DAC's).
2. Description of Related Art
A digital-to-analog converter (DAC) usually includes a resistor network and an array of switches or multiplexer circuit. The N-bit digital input is applied to the multiplexer circuit to control the switches. The size of the array of switches is a function of the number of input bits N. A large value of N may result in a prohibitively large array size. To reduce the complexity of the switch array, many DAC's utilize a multi stage switching scheme.
FIG. 1 illustrates a prior art 2-stage DAC. The prior art DAC 100 includes a first resistor network 110, a first stage multiplexer circuit 120, a second resistor network 130, and a second stage multiplexer circuit 140. The N-bit digital input is composed of J most significant bits (MSB's) and K least significant bits (LSB's).
The first resistor network 110 includes a series of resistors R.sub.1,0, R.sub.1,1, . . . R.sub.1,2.sup.J whose values are selected to provide 2.sup.J voltage values. The first stage multiplexer circuit 120 selects one out of the 2.sup.J voltage values as provided by the first resistor network 110. The multiplexer circuit 120 is controlled by the J most significant bits (MSB's) of the N-bit input. The second resistor network 130 divides the voltage output of the first stage multiplexer circuit 120 into further 2.sup.K voltage values. The second stage multiplexer circuit 140 selects one out of the 2.sup.K voltage values to produce the final output voltage. The second stage multiplexer circuit 140 is controlled by the K least significant bits (LSB's) of the N-bit input.
To reduce the well understood "loading effect" of the second resistor network, a high unit resistance ratio between the second and the first resistor networks is required, which tends to increase the size of the converter and significantly impact the speed performance. There has been design which inserts two unit gain buffers in between the first and the second resistor networks. This method reduces the loading effect, but does not solve problems caused by the offset of the buffers.
Although the 2-stage DAC reduces the hardware complexity from the single stage DAC, the amount of hardware is still high. There are two resistor networks and two multiplexer circuits. For medium to high resolution DACs, it is desirable to reduce the hardware complexity further.
Therefore there is a need in the technology to provide a simple and efficient technique to reduce the hardware complexity in DAC.